1. Field
Example embodiments relate to a semiconductor memory device and, for example, to a semiconductor memory device configured to repair failures in memory cells caused after a packaging process, and/or a redundancy method of the same.
2. Description of Related Art
A conventional semiconductor memory device may perform a primary test on memory cells at a wafer level and program a defective address into a redundancy circuit included therein if a defective memory cell is detected. If the defective address is applied in a normal operation of the semiconductor memory device, the defective memory cell may be replaced with a redundancy memory cell. Accordingly, a defective semiconductor memory device may be repaired and/or determined to be non-defective.
A semiconductor memory device, which is determined to be non-defective at a wafer level, may be packaged through a packaging process. The packaged semiconductor memory device may perform the test on the memory cells at a package level. If a defective memory cell is found at the package level the semiconductor memory device may be finally decided as a defective semiconductor memory device.
In many cases, only one or two memory cells of the semiconductor memory device are defective at a package level. Accordingly, many attempts at repairing the defective memory cells have been made and many related techniques have been disclosed.
However, in many conventional semiconductor memory devices, after a test is performed at a package level under the control of a test apparatus, an address of a defective memory cell may be stored in the test apparatus. The address of the defective memory cell may be applied by the test apparatus to the semiconductor memory device in a repair operation so that the address of the defective memory cell may be programmed. Accordingly, the semiconductor memory device that is decided as a defective device at the package level may be repaired and/or determined to be non-defective.
In other words, in many of the conventional semiconductor memory devices, after the address of the memory cell that is defective at the package level is stored in the test apparatus, the address of the defective memory cell needs to be applied by the test apparatus to the semiconductor memory device and programmed.